Peer-Reviewed Journal Details
Mandatory Fields
Pande, S,Morgan, F,Smit, G,Bruintjes, T,Rutgers, J,McGinley, B,Cawley, S,Harkin, J,McDaid, L
2013
September
Parallel Computing
Fixed latency on-chip interconnect for hardware spiking neural network architectures
Published
()
Optional Fields
Network on Chip (NoC) Spiking Neural Networks (SNN) Synaptic connectivity Latency jitter NEURONS PLATFORM DESIGN
39
357
371
Information in a Spiking Neural Network (SNN) is encoded as the relative timing between spikes. Distortion in spike timings can impact the accuracy of SNN operation by modifying the precise firing time of neurons within the SNN. Maintaining the integrity of spike timings is crucial for reliable operation of SNN applications. A packet switched Network on Chip (NoC) infrastructure offers scalable connectivity for spike communication in hardware SNN architectures. However, shared resources in NoC architectures can result in unwanted variation in spike packet transfer latency. This packet latency jitter distorts the timing information conveyed on the synaptic connections in the SNN, resulting in unreliable application behaviour.This paper presents a SystemC simulation based analysis of the synaptic information distortion in NoC based hardware SNNs. The paper proposes a fixed spike transfer latency ring topology interconnect for spike communication between neural tiles, using a novel time-stamped spike broadcast flow control scheme. The proposed architectural technique is evaluated using spike rates employed in previously reported mesh topology NoC based hardware SNN applications, which exhibited spike latency jitter over NoC paths. Results indicate that the proposed interconnect offers fixed spike transfer latency and eliminates the associated information distortion.The paper presents the micro-architecture of the proposed ring router. The FPGA validated ring interconnect architecture has been synthesised using 65 nm low-power CMOS technology. Silicon area comparisons for various ring sizes are presented. Scalability of the proposed architecture has been addressed by employing a hierarchical NoC architecture. (C) 2013 Elsevier B.V. All rights reserved.
DOI 10.1016/j.parco.2013.04.010
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