Coupled inductors offer significant advantages over their uncoupled counterparts; however, with these advantages come a number of additional design caveats. The factors affecting the design and optimization of coupled stripline microinductors for PwrSoC applications are outlined, which include device area, the number of coupled phases, duty cycle, paralleling of coupled inductors, switching frequency, as well as thermal and saturation constraints. Results of this analysis are presented and discussed along with guidelines for the design of coupled stripline microinductors, which show that paralleling coupled inductors is the best route toward higher output current. Analytical models predict a peak inductor efficiency of 86.8% and 86.3% for fabricated 3 and 5-phase coupled stripline microinductors with an Ni-45 Fe-55 core, respectively. Models are verified by measurements on prototype 3 and 5-phase converters with parallel coupled stripline microinductors over a range of operating conditions.